HD64F2145 Datasheet, PDF (486/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to
0.
Slave receive mode
SCL
(master output) 8 9
SDA
(slave output)
A
[2]
SDA
(master output) _R/
IRIC
Slave transmit mode
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[4]
A
1
2
Bit 7 Bit 6
Data 2
ICDRE
ICDR
Data 1
Data 2
User processing
[3] IRIC clear
[3] ICDR write
[3] IRIC clear
[5] IRIC clear
[5] ICDR write
Figure 16.25 Example of Slave Transmit Mode Operation Timing
(MLS = 0)
16.4.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 16.26 to 16.28 show the IRIC set timing and SCL control.
Rev. 2.0, 08/02, page 446 of 788