HD64F2145 Datasheet, PDF (643/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

transition to verify mode can be made. The error protection state can be cancelled by a reset or in
hardware standby mode.
23.10 Interrupts during Flash Memory Programming/Erasing
In order to give the highest priority to programming/erasing operations, disable all interrupts
including NMI input during flash memory programming/erasing (the P or E bit in FlMCR1 is set
to 1) or boot program execution*¹.
1. If an interrupt is generated during programming/erasing, operation in accordance with the
program/erase algorithm is not guaranteed.
2. CPU runaway may occur because normal vector reading cannot be performed in interrupt
exception handling during programming/erasing*².
3. If an interrupt occurs during boot program execution, the normal boot mode sequence cannot
be executed.
Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming
control program has completed programming.
2. The vector may not be read correctly for the following two reasons:
If flash memory is read while being programmed or erased (while the P or E bit in
FLMCR1 is set to 1), correct read data will not be obtained (undefined values will be
returned).
If the interrupt entry in the vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Rev. 2.0, 08/02, page 603 of 788