HD64F2145 Datasheet, PDF (459/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W Description
3 CLR3
1
W*² IIC Clear 3 to 0
2 CLR2
1
1 CLR1
1
0 CLR0
1
Controls initialization of the internal state of IIC_0 and
IIC_1.
00--: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal latch cleared
0111: IIC_0 and IIC_1 internal latches cleared
1---: Invalid setting
When a write operation is performed on these bits, a clear
signal is generated for the internal latch circuit of the
corresponding module, and the internal state of the IIC
module is initialized.
These bits can only be written to; they are always read as
1. Write data to this bit is not retained.
To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not
use a bit manipulation instruction such as BCLR.
When clearing is required again, all the bits must be written
to in accordance with the setting.
If the function of these bits is not used, set all of the CLR3
to CLR0 bits to 1 when writing to DDCSWR.
Notes: 1. Only 0 can be written, to clear the flag.
2. This bit is always read as 1.
Rev. 2.0, 08/02, page 419 of 788