HD64F2145 Datasheet, PDF (530/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• HICR2
Bit
7 to 3
Bit
Name

2
IBFIE4
1
IBFIE3
0

Initial
Value
All 1
R/W
Slave Host


0
R/W 
0
R/W 
0


Description
Reserved
These bits are always read as 1, and cannot be
modified.
Input Data Register Full Interrupt Enable 4
Enables or disables the IBF4 interrupt to the
internal CPU.
0: Input data register (IDR_4) reception
completed interrupt request disabled
1: Input data register (IDR_4) reception
completed interrupt request enabled
Input Data Register Full Interrupt Enable 3
Enables or disables the IBF3 interrupt to the
internal CPU.
0: Input data register (IDR_3) reception
completed interrupt request disabled
1: Input data register (IDR_3) reception
completed interrupt request enabled
Reserved
The initial value should not be changed.
Rev. 2.0, 08/02, page 490 of 788