HD64F2145 Datasheet, PDF (512/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

KCLK
(pin state)
KD
(pin state)
KCLK
(input)
KCLK
(output)
1
2
3
Start
bit
0
1
KB7 to KB0 Previous data KB0 KB1
PER
KBS
KBF
Flag cleared
Receive processing/
error handling
9
10
11
7 Parity bit Stop bit
Automatic I/O inhibit
Receive data
[1] [2] [3]
[4] [5]
[6]
Figure 17.4 Receive Timing
17.4.2 Transmit Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6.
Rev. 2.0, 08/02, page 472 of 788