HD64F2145 Datasheet, PDF (265/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

9.4 Operation
The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a
resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse.
Table 9.4 Duty Cycle of Basic Pulse
Upper 4 Bits
0000
Basic Pulse Waveform (Internal)
0 1 2 3 4 5 6 7 8 9 ABCDEF 0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An
additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the
rising edge of a basic pulse. When the upper four bits of PWDR are 0000, there is no rising edge
of the basic pulse, but the timing for adding pulses is the same. Table 9.5 shows the positions of
the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional
pulse timing.
Rev. 2.0, 08/02, page 225 of 788