HD64F2145 Datasheet, PDF (227/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

8.10.1 Port 9 Data Direction Register (P9DDR)
P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis.
Initial
Bit Bit Name Value R/W Description
7
P97DDR 0
W
P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2
6
P96DDR 1/0* W
and 3).
5
P95DDR 0
W
Modes 1, 2, and 3 (EXPE = 1):
4
P94DDR 0
W
Pin P97 functions as a bus control input (:$,7), the IIC_0
I/O pin (SDA0), or an I/O port, according to the wait mode
3
P93DDR 0
W
setting. When P97 functions as an I/O port, it becomes an
2
P92DDR 0
1
P91DDR 0
0
P90DDR 0
W
output port when P97DDR is set to 1, and an input port
when P97DDR is cleared to 0.
W
Pin P96 functions as the ø output pin when P96DDR is set
W
to 1, and as the subclock input (EXCL) or an input port
when P96DDR is cleared to 0.
Pins P95 to P93 automatically become bus control outputs
($6/,26, +:5, 5'), regardless of the input/output
direction indicated by P95DDR to P93DDR.
Pins P92 and P91 become output ports when P92DDR
and P91DDR are set to 1, and input ports when P92DDR
and P91DDR are cleared to 0.
When the ABW bit in WSCR is cleared to 0, pin P90
becomes a bus control output (/:5), regardless of the
input/output direction indicated by P90DDR. When the
ABW bit is 1, pin P90 becomes an output port if P90DDR
is set to 1, and an input port if P90DDR is cleared to 0.
Modes 2 and 3 (EXPE = 0):
When the corresponding P9DDR bits are set to 1, pin P96
functions as the ø output pin and pins P97 and P95 to P90
become output ports. When P9DDR bits are cleared to 0,
the corresponding pins become input ports.
Note:* The initial value of P96DDR is 1 (mode 1) or 0 (modes 2 and 3).
Rev. 2.0, 08/02, page 187 of 788