HD64F2145 Datasheet, PDF (176/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Interrupt controller
DTC
Interrupt
request
Internal address bus
On-chip RAM
CPU interrupt
request
Internal data bus
Legend:
MRA, MRB
: DTC mode register A, B
CRA, CRB
: DTC transfer count register A, B
SAR
: DTC source address register
DAR
: DTC destination register
DTCERA to DTCERE : DTC enable registers A to E
DTVECR
: DTC vector register
Figure 7.1 Block Diagram of DTC
7.2 Register Descriptions
The DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt
source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to on-chip RAM.
• DTC enable registers A to E (DTCERA to DTCERE)
• DTC vector register (DTVECR)
Rev. 2.0, 08/02, page 136 of 788