HD64F2145 Datasheet, PDF (812/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
14.3.2 Timer
Control/Status Register
(TCSR)
• TCSR_1
Page Revisions (See Manual for Details)
331 CKS2 to CKS0, Clock Select 2 to 0
(Error)
Selects the clock source to be input to TCNT. The overflow
cycle for ø = 25 MHz and øSUB = 32.768 MHz is enclosed in
parentheses.
(Correction)
Selects the clock source to be input to TCNT. The overflow
cycle for ø = 10 MHz and øSUB = 32.768 kHz is enclosed in
parentheses.
When PSS = 0:
(Error)
000: ø/2 (frequency: 20.4 µs)
001: ø/64 (frequency: 655.3 µs)
010: ø/128 (frequency: 1.3 ms)
011: ø/512 (frequency: 5.2 ms)
100: ø/2048 (frequency: 20.9 ms)
101: ø/8192 (frequency: 83.8 ms)
110: ø/32768 (frequency: 335.5 ms)
111: ø/131072 (frequency: 1.34 s)
(Correction)
000: ø/2 (frequency: 51.2 µs)
001: ø/64 (frequency: 1.64 ms)
010: ø/128 (frequency: 3.28 ms)
011: ø/512 (frequency: 13.1 ms)
100: ø/2048 (frequency: 52.4 ms)
101: ø/8192 (frequency: 209.7 ms)
110: ø/32768 (frequency: 0.84 s)
111: ø/131072 (frequency: 3.36 s)
Rev. 2.0, 08/02, page 772 of 788