HD64F2145 Datasheet, PDF (654/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

25.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (ø) or medium-speed clock (ø/2, ø/4, ø/8, ø/16, or ø/32) by the SCK2 to SCK0 bits in
SBYCR.
25.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in
P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
Subclock input conditions are shown in table 25.5. When the subclock is not used, subclock input
should not be enabled.
Table 25.5 Subclock Input Conditions
Item
Symbol
Subclock input pulse width t
EXCLL
low level
Subclock input pulse width t_EXCLH
high level
Subclock input rising time t_EXCLr
Subclock input falling time t_EXCLf
Vcc = 2.7 to 5.5 V
Min
Typ
Max
—
15.26 —
—
15.26 —
—
—
10
—
—
10
Measurement
Unit Condition
µs
Figure 25.7
µs
ns
ns
EXCL
t_EXCLH
t_EXCLL
V_CC × 0.5
t_EXCLr
t_EXCLf
Figure 25.7 Subclock Input Timing
25.6 Subclock Waveform Forming Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided ø
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
Rev. 2.0, 08/02, page 614 of 788