HD64F2145 Datasheet, PDF (666/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

When the 67%< pin is driven low, medium-speed mode is cancelled and a transition is made to
hardware standby mode.
Figure 26.2 shows an example of medium-speed mode timing.
ø,
peripheral module clock
Bus master clock
Medium-speed mode
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 26.2 Medium-Speed Mode Timing
26.4 Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU
operation stops but the peripheral modules do not stop. The contents of the CPU’s internal
registers are retained.
Sleep mode is exited by any interrupt, the 5(6#pin, or the 67%< pin.
When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode
is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU.
Setting the 5(6 pin level low cancels sleep mode and selects the reset state. After the oscillation
stabilization time has passed, driving the 5(6 pin high causes the CPU to start reset exception
handling.
When the 67%< pin level is driven low, sleep mode is cancelled and a transition is made to
hardware standby mode.
Rev. 2.0, 08/02, page 626 of 788