HD64F2145 Datasheet, PDF (152/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.8.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
EEPMOV.W
MOV.W
R4,R4
BNE
L1
5.8.4 Setting on Product Incorporating DTC
When a product, in which a DTC is incorporated, is used in the following settings, the
corresponding flag bit is not automatically cleared even when exception handing, which is a clear
condition, is executed and the bit is held at 1.
1. When DTCEA3 is set to 1(ADI is set to an interrupt source), IRQ4F flag is not automatically
cleared.
2. When DTCEA2 is set to 1(ICIA is set to an interrupt source), IRQ5F flag is not automatically
cleared.
3. When DTCEA1 is set to 1(ICIB is set to an interrupt source), IRQ6F flag is not automatically
cleared.
4. When DTCEA0 is set to 1(OCIA is set to an interrupt source), IRQ7F flag is not automatically
cleared.
When activation interrupt sources of DTC and IRQ interrupts are used with the above
combinations, clear the interrupt flag by software in the interrupt handling routine of the
corresponding IRQ.
5.8.5 IRQ Status Register (ISR)
According to the pin status after a reset, IRQnF may be set to 1, so ISR should be read after a reset
to write 0. (n = 7 to 0)
Rev. 2.0, 08/02, page 112 of 788