HD64F2145 Datasheet, PDF (181/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

diagram of DTC activation source control. For details on the interrupt controller, see section 5,
Interrupt Controller.
Source flag cleared
Clear
DTCER
Select
Clear
controller
Clear request
On-chip
peripheral
module
DTC
IRQ interrupt _Interrupt
request
DTVECR
Interrupt controller
Interrupt mask
CPU
Figure 7.2 Block Diagram of DTC Activation Source Control
7.4 Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF).
Register information should be located at an address that is a multiple of four within the range.
The method for locating the register information in address space is shown in figure 7.3. Locate
MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 7.3, and the register information start address should be located at the
vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the
start address of the register information from the vector table set for each activation source, and
then reads the register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal and advanced modes; a 2-byte
unit is used in both cases. Specify the lower two bits of the register information start address.
Rev. 2.0, 08/02, page 141 of 788