HD64F2145 Datasheet, PDF (533/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 18.2 shows the conditions for setting and clearing the STR flags.
Table 18.2 Set/Clear Timing for STR Flags
Flag
Setting Condition
Clearing Condition
C/'
Rising edge of host’s write signal Rising edge of host’s write signal (,2:) when
(,2:) when HA0 is high
HA0 is low
IBF*
Rising edge of host’s write signal
(,2:) when writing to IDR1
Falling edge of slave’s internal read signal when
reading IDR1
OBF
Falling edge of slave’s internal write Rising edge of host’s read signal (,25) when
signal when writing to ODR1
reading ODR1
Note:* The IBF flag setting and clearing conditions are different when the fast A20 gate is used.
For details see table 18.5.
18.4 Operation
18.4.1 Host Interface Activation
The host interface is activated by setting the HI12E bit in SYSCR2 to 1 in single-chip mode.
When the host interface is activated, all related I/O ports (data port 3, control ports 8 and 9, and
host interrupt request port 4) become dedicated host interface ports. Setting the CS3E bit and
CS4E bit to 1 enables the number of host interface channels to be extended to four, and makes the
channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated
host interface port.
Rev. 2.0, 08/02, page 493 of 788