HD64F2145 Datasheet, PDF (19/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface (IIC) (Optional) ...................................................393
16.1 Features .............................................................................................................................393
16.2 Input/Output Pins ..............................................................................................................396
16.3 Register Descriptions.........................................................................................................397
16.3.1 I²C Bus Data Register (ICDR)..............................................................................397
16.3.2 Slave Address Register (SAR) .............................................................................398
16.3.3 Second Slave Address Register (SARX)..............................................................399
16.3.4 I²C Bus Mode Register (ICMR) ...........................................................................401
16.3.5 I²C Bus Control Register (ICCR) .........................................................................404
16.3.6 I²C Bus Status Register (ICSR) ............................................................................414
16.3.7 DDC Switch Register (DDCSWR) ......................................................................418
16.3.8 I²C Bus Extended Control Register (ICXR) .........................................................420
16.4 Operation...........................................................................................................................424
16.4.1 I²C Bus Data Format.............................................................................................424
16.4.2 Initialization .........................................................................................................426
16.4.3 Master Transmit Operation ..................................................................................426
16.4.4 Master Receive Operation ....................................................................................430
16.4.5 Slave Receive Operation ......................................................................................437
16.4.6 Slave Transmit Operation.....................................................................................444
16.4.7 IRIC Setting Timing and SCL Control.................................................................446
16.4.8 Automatic Switching from Formatless Mode to I²C Bus Format.........................449
16.4.9 Operation Using DTC ..........................................................................................450
16.4.10 Noise Canceler .....................................................................................................451
16.4.11 Initialization of Internal State...............................................................................452
16.5 Interrupt Sources ...............................................................................................................454
16.6 Usage Notes.......................................................................................................................454
16.6.1 Module Stop Mode Setting...................................................................................463
Section 17 Keyboard Buffer Controller.............................................................465
17.1 Features .............................................................................................................................465
17.2 Input/Output Pins ..............................................................................................................466
17.3 Register Descriptions.........................................................................................................467
17.3.1 Keyboard Control Register H (KBCRH)..............................................................467
17.3.2 Keyboard Control Register L (KBCRL) ..............................................................469
17.3.3 Keyboard Data Buffer Register (KBBR)..............................................................470
17.4 Operation...........................................................................................................................471
17.4.1 Receive Operation ................................................................................................471
17.4.2 Transmit Operation ..............................................................................................472
17.4.3 Receive Abort.......................................................................................................475
17.4.4 KCLKI and KDI Read Timing .............................................................................477
17.4.5 KCLKO and KDO Write Timing .........................................................................477
17.4.6 KBF Setting Timing and KCLK Control .............................................................478
17.4.7 Receive Timing ....................................................................................................479
Rev. 2.0, 08/02, page xvii of xxxviii