HD64F2145 Datasheet, PDF (800/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Page
Section 3 MCU Operating 66
Modes
3.2.2 System Control
Register (SYSCR)
Section 4 Exception
84
Handling
4.7 Usage Note
Figure 4.3 Operation
when SP Value is Odd
Revisions (See Manual for Details)
Description of bit 1 amended.
(Error) keyboard buffer controller
(Correction) keyboard matrix interrupt
Corrected.
CCR
SP
SP
PC
SP
Address
R1L
H'FFEFFA
H'FFEFFB
PC
H'FFEFFC
H'FFEFFD
H'FFEFFF
TRAPA instruction executed
MOV.B R1L, @-ER7 executed
SP set to H'FFEFFF
Data saved above SP
Contents of CCR lost
Section 5 Interrupt
86
Controller
5.1 Features
Figure 5.1 Block Diagram
of Interrupt Controller
5.3.1 Interrupt Control 88
Registers A to C (ICRA to
ICRC)
5.3.6 IRQ Status Register 92
(ISR)
(Error)
KIN input
WUE input
KMIMR WUEMR
KIM and WUE
input
(Correction)
KMIMR WUEMR
KIN input
WUE input
KIN and WUE
input
(Error) The ICR registers set interrupt control levels for
interrupts other than NMI.
(Correction) The ICR registers set interrupt control levels for
interrupts other than NMI and address breaks.
Bits 7 to 0
R/W
R/(W)*²
Description
When interrupt exception handling is executed when low-level
detection is set and ,54Q input is high (n = 7 to 0)*¹
When IRQn interrupt exception handling is executed when falling-
edge, rising-edge, or both-edge detection is set*¹
Notes: 1.
2.
When a product, in which a DTC is incorporated, is used,
the corresponding flag bit is not automatically cleared
even when exception handing is executed. For details,
refer to section 5.8.4, Setting on a Product Incorporating
DTC.
Only 0 can be written, for flag clearing.
Rev. 2.0, 08/02, page 760 of 788