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| HD64F2145 Datasheet, PDF (172/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer | |||
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Full access
Burst access
T1
T2
T3
T1
T2
T1
T2
Ã
Address bus
Only lower address changes
/
(IOSE = 0)
Data bus
Read data
Read data
Read data
Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)
Full access
T1
T2
Burst access
T1
T1
Ã
Address bus
Only lower
address changes
/
(IOSE = 0)
Data bus
Read data
Read data Read data
Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
6.6.2 Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the :$,7 pin
can be used in the initial cycle (full access) of the burst ROM interface. For details, see section
6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle.
Rev. 2.0, 08/02, page 132 of 788
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