HD64F2145 Datasheet, PDF (528/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18.3.2 Host Interface Control Register (HICR)
Host Interface Control Register 2 (HICR2)
HICR controls host interface channel 1 and 2 interrupts and the fast A20 gate function. HICR2
controls host interface channel 3 and 4 interrupts.
• HICR
Bit
7 to 3
Bit
Name

2
IBFIE2
1
IBFIE1
Initial
Value
All 1
R/W
Slave Host


0
R/W 
0
R/W 
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Input Data Register Full Interrupt Enable 2
Enables or disables the IBF2 interrupt to the
internal CPU.
0: Input data register (IDR_2) reception
completed interrupt request disabled
1: Input data register (IDR_2) reception
completed interrupt request enabled
Input Data Register Full Interrupt Enable 1
Enables or disables the IBF1 interrupt to the
internal CPU.
0: Input data register (IDR_1) reception
completed interrupt request disabled
1: Input data register (IDR_1) reception
completed interrupt request enabled
Rev. 2.0, 08/02, page 488 of 788