HD64F2145 Datasheet, PDF (342/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit
Bit Name
3
HFINV
2
VFINV
1
HIINV
0
VIINV
Legend
X: Don’t care
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Input Synchronization Signal Inversion
These bits select inversion of the input phase of the
spare horizontal synchronization signal (HFBACKI),
the spare vertical synchronization signal (VFBACKI),
the horizontal synchronization signal (HSYNCI),
composite synchronization signal (CSYNCI), and the
vertical synchronization signal (VSYNCI).
• HFINV
0: The HFBACKI pin state is used directly as the
HFBACKI input
1: The HFBACKI pin state is inverted before use as
the HFBACKI input
• VFINV
0: The VFBACKI pin state is used directly as the
VFBACKI input
1: The VFBACKI pin state is inverted before use as the
VFBACKI input
• HIINV
0: The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
1: The HSYNCI and CSYNCI pin states are inverted
before use as the HSYNCI and CSYNCI inputs
• VIINV
0: The VSYNCI pin state is used directly as the
VSYNCI input
1: The VSYNCI pin state is inverted before use as the
VSYNCI input
Table 13.2 Synchronization Signal Connection Enable
Bit 5
SCONE
0
1
Description
Mode
FTIA FTIB FTIC
FTID TMCI1 TMRI1
Normal connection (Initial value) FTIA FTIB FTIC
input input input
FTID TMCI1 TMRI1
input input input
Synchronization signal
connection mode
IVI
TMO1 VFBACKI IHI IHI
IVI
signal signal input
signal signal inverse
signal
Rev. 2.0, 08/02, page 302 of 788