HD64F2145 Datasheet, PDF (472/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Master transmit mode
Master receive mode
SCL
(master output)
9
SDA
A
(slave output)
SDA
(master output)
IRIC
SCL is fixed low until ICDR is read
SCL is fixed low until ICDR is read
1
2
3
4
5
6
7
8
9
12
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3]
A
Bit 7 Bit 6
Data 2
IRTR
ICDRF
ICDRR
Undefined value
Data 1
User processing
[1] TRS=0 clear
[1] IRIC clear
[2] IRIC read
(Dummy read)
[4] IRIC clear
[5] ICDR read
(Data 1)
Figure 16.12 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)
SCL
(master output) ⁷
8
SDA
(slave output)
SDA
(master output)
Bit 1 Bit 0
Data 2
SCL is fixed low until ICDR is read
SCL is fixed low until _{Stop condition generation}
stop condition is issued
9
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[3]
Data 3
[8]
A
A
IRIC
IRTR
ICDRF
ICDRR
Data 1
Data 2
Data 3
User processing [4] IRIC clear
[7] ICDR read
(Data 2)
[6] Set ACKB = 1
[9] IRIC clear
[10] ICDR read
(Data 3)
[11] Set BBSY=0 and
SCP=0
(Stop condition instruction issuance)
Figure 16.13 Example of Stop Condition Issuance Operation Timing
in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
Receive Operation Using the Wait Function:
Figures 16.14 and 16.15 show the sample flowcharts for the operations in master receive mode
(WAIT = 1).
Rev. 2.0, 08/02, page 432 of 788