HD64F2145 Datasheet, PDF (540/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 18.9 HIRQ Setting/Clearing Conditions
Host Interrupt
Signal
Setting Condition
HIRQ11
(P43)
Internal CPU reads 0 from bit P43DR,
then writes 1
HIRQ1
(P44)
Internal CPU reads 0 from bit P44DR,
then writes 1
HIRQ12
(P45)
Internal CPU reads 0 from bit P45DR,
then writes 1
HIRQ3
(PB0)
Internal CPU reads 0 from bit PB0ODR,
then writes 1
HIRQ4
(PB1)
Internal CPU reads 0 from bit PB1ODR,
then writes 1
Clearing Condition
Internal CPU writes 0 in bit P43DR, or
host reads output data register_2
(ODR_2)
Internal CPU writes 0 in bit P44DR, or
host reads output data register_1
(ODR_1)
Internal CPU writes 0 in bit P45DR, or
host reads output data register_1
(ODR_1)
Internal CPU writes 0 in bit PB0ODR,
or host reads output data register_3
(ODR_3)
Internal CPU writes 0 in bit PB1ODR,
or host reads output data register_4
(ODR_4)
Slave CPU
Master CPU
Write to ODR
Write 1 to P4DR
P4DR = 0?
No
Yes
All bytes
No
transferred?
Yes
HIRQ output high
HIRQ output low
Interrupt initiation
ODR read
Hardware operations
Software operations
Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2)
HIRQ Setting/Clearing Conflict: If there is conflict between a P4DR or PBODR read/write by
the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the
Rev. 2.0, 08/02, page 500 of 788