HD64F2145 Datasheet, PDF (100/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

2.9 Usage Notes
2.9.1 Note on TAS Instruction Usage
When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.
The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers.
When the TAS instruction is used as a user-defined intrinsic function, use registers ER0, ER1,
ER4 and ER5.
2.9.2 Note on STM/LDM Instruction Usage
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored
by one STM/LDM instruction. The following ranges can be specified in the register list.
Two registers: ER0—ER1, ER2—ER3, or ER4—ER5
Three registers: ER0—ER2 or ER4—ER6
Four registers: ER0—ER3
The STM/LDM instruction including ER7 is not generated by the Hitachi H8S and H8/300 series
C/C++ compilers.
2.9.3 Note on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where a register containing a
write-only bit is used or a bit is directly manipulated for a port, because this may rewrite data of a
bit other than the bit to be manipulated.
Example: The BCLR instruction is executed for DDR in port 4.
P47 and P46 are input pins, with a low-level signal input at P47 and a high-level signal input at
P46. P45 to P40 are output pins and output low-level signals. The following shows an example in
which P40 is set to be an input pin with the BCLR instruction.
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