HD64F2145 Datasheet, PDF (658/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

26.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit Bit Name Initial Value R/W Description
7 SSBY 0
R/W Software Standby
Specifies the operating mode to be entered after executing
the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode, subactive mode, or
watch mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode
1: Shifts to watch mode or high-speed mode
Note that the SSBY bit is not changed even if a mode
transition occurs by an interrupt.
6 STS2 0
R/W Standby Timer Select 2 to 0
5 STS1 0
4 STS0 0
R/W Selects the wait time for clock stabilization from clock
R/W ^{oscillation start when canceling software standby mode,}
watch mode, or subactive mode. Select a wait time of 8 ms
(oscillation stabilization time) or more, depending on the
operating frequency. Table 26.1 shows the relationship
between the STS2 to STS0 values and wait time.
With an external clock, there are no specific wait
requirements. Normally the minimum value is
recommended.
3
0
R
Reserved
This bit is always read as 0, and cannot be modified.
Rev. 2.0, 08/02, page 618 of 788