HD64F2145 Datasheet, PDF (802/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Page Revisions (See Manual for Details)
5.6.5 DTC Activation by 106 _Corrected.
Interrupt
CPU interrupt
Figure 5.8 DTC and
Interrupt Controller
Determination of
priority
request vector
number
I,UI
CPU
5.7 Address Break
Section 6 Bus Controller
6.5.4 Wait Control
Figure 6.13 Example of
Wait State Insertion
Timing (Pin Wait Mode)
107 _Added.
to 110
131 _Corrected.
Write
,
Data bus
Write data
6.7 Idle Cycle
133
Figure 6.16 Examples of
Idle Cycle Operation
Corrected.
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
Ø
Address bus
Ø
Address bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
,
,
Data bus
Data bus
Data collision
Long output floating time
(a) No idle cycle insertion
(b) Idle cycle insertion
Section 7 Data Transfer 135
Controller (DTC)
7.1 Features
7.2.2 DTC Mode Register 138
B (MRB)
Deleted.
• Usable for scan operations of CIN7 to CIN0
• DTC operates in high-speed mode even when the LSI is in
medium-speed mode
Description of bit 6 (DISEL) added.
When this bit is set to 1, a CPU interrupt request is generated
every time data transfer ends (the DTC clears the interrupt
source flag for the activation source). When this bit is cleared
to 0, a CPU interrupt request is generated only when the
specified number of data transfer ends (the DTC does not
clear the interrupt source flag for the activation source).
Rev. 2.0, 08/02, page 762 of 788