HD64F2145 Datasheet, PDF (492/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Sampling clock
SCL or
SDA input
signal
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Internal
SCL or
SDA
signal
Sampling
clock
System clock
cycle
Figure 16.29 Block Diagram of Noise Canceler
16.4.11 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch
Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
and ICDRF flags), DDCSWR)
• Internal latches used to retain register read information for setting/clearing flags in ICMR,
ICCR, ICSR, and DDCSWR
• The value of the ICMR bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Rev. 2.0, 08/02, page 452 of 788