HD64F2145 Datasheet, PDF (609/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 21.3 A/D Conversion Time (Single Mode)
CKS = 0
Item
Symbol min typ max
A/D conversion start delay time t_D
10
—
17
Input sampling time
t
—
63
—
SPL
A/D conversion time
t_CONV
259 —
266
Note:* Values in the table indicate the number of states.
CKS = 1
min typ max
6
—
9
—
31
—
131 —
134
21.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B’11 in
ADCR, external trigger input is enabled at the $'75* pin. A falling edge at the $'75* pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit has been set to 1 by software. Figure 21.4 shows the
timing.
ø
Internal trigger
signal
ADST
A/D conversion
Figure 21.4 External Trigger Input Timing
21.5 Interrupt Sources
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1
after A/D conversion is completed.
Rev. 2.0, 08/02, page 569 of 788