HD64F2145 Datasheet, PDF (108/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value
3
FLSHE
0
2—
0
1 ICKS1
0
0 ICKS0
0
R/W
R/W
R/(W)
R/W
R/W
Description
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FLMCR1, FLMCR2, EBR1, EBR2), control
registers in power-down state (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control registers of on-
chip peripheral modules (PCSR, SYSCR2).
0: Registers in power-down state and control
registers of on-chip peripheral modules are accessed
in an area from H’(FF)FF80 to H’(FF)FF87.
1: Control registers of flash memory are accessed in
an area from H’(FF)FF80 to H’(FF)FF87.
Reserved
The initial value should not be changed.
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, refer to section 12.3.4, Timer
Control Register (TCR).
Rev. 2.0, 08/02, page 68 of 788