HD64F2145 Datasheet, PDF (453/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

MST TRS BBSY ESTP STOP IRTR AASX AL
0
0
1
0
0
—
—
—
AAS
—
ADZ
—
ACKB
—
ICDRF
1
0
0
1
0
0
—
—
0↓
0↓
0↓
—
0↓
0
0
1
0
0
1↑/0 —
0
0
0
—
1↑
*²
0
—
0↓
1↑/0 0/1↑ —
—
—
—
—
—
—
*³
*³
Legend
0: 0-state retained
1: 1-state retained
—: Previous state retained
0↓: Cleared to 0
1↑: Set to 1
Notes: 1. Set to 1 when 1 is received as a R/: bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
ICDRE
—
—
—
0↓
State
Reception end
with ICDRF=1
ICDR read
with the above
state
Automatic
data transfer
from ICDRS to
ICDRR with
the above
state
Stop condition
detected
Rev. 2.0, 08/02, page 413 of 788