HD64F2145 Datasheet, PDF (500/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

9. Note on when I²C bus interface stop condition instruction is issued
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
SCL
SDA
IRIC
9th clock
VIH
Secures a high period
SCL is detected as low
because the rise of the
waveform is delayed
Stop condition generation
[1] SCL = low determination [2] Stop condition instruction issuance
Figure 16.32 Stop Condition Issuance Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
10. Note on IRIC flag clear when the wait function is used
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I²C bust interface
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
Secures a high period
SCL
VIH
SCL = low detected
SDA
IRIC
[1] SCL = low determination
[2] IRIC clear
Figure 16.33 IRIC Flag Clearing Timing When WAIT = 1
Rev. 2.0, 08/02, page 460 of 788