HD64F2145 Datasheet, PDF (583/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 19.5 shows the scope of the host interface pin shutdown.
Table 19.5 Scope of Host Interface Pin Shutdown
Abbreviation Port
Scope of
Shutdown I/O
Notes
LAD3 to LAD0 P33–P30 O
I/O
Hi-Z
/)5$0(
P34
O
Input
Hi-Z
/5(6(7
P35
×
Input
LPC hardware reset function is active
LCLK
P36
O
Input
Hi-Z
SERIRQ
P37
O
I/O
Hi-Z
LSCI
PB1
∆
I/O
Hi-Z, only when LSCIE = 1
/60,
PB0
∆
I/O
Hi-Z, only when LSMIE = 1
30(
P80
∆
I/O
Hi-Z, only when PMEE = 1
GA20
P81
∆
I/O
Hi-Z, only when FGA20E = 1
&/.581
P82
O
I/O
Hi-Z
/3&3'
P83
×
Input
Needed to clear shutdown state
Legend
O: Pin that is shutdown by the shutdown function
∆: Pin that is shutdown only when the LPC function is selected by register setting
×: Pin that is not shutdown
In the LPC shutdown state, the LPC’s internal state and some register bits are initialized. The
order of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by 67%< or 5(6 pin input, or WDT0 overflow)
 All register bits, including bits LPC3E to LPC1E, are initialized.
2. LPC hardware reset (reset by /5(6(7 pin input)
 LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
 SDWNE and SDWNB bits are cleared to 0.
4. LPC hardware shutdown
 SDWNB bit is cleared to 0.
5. LPC software shutdown
Rev. 2.0, 08/02, page 543 of 788