HD64F2145 Datasheet, PDF (551/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• HICR1
R/W
Bit Bit Name Initial Value Slave Host Description
7 LPCBSY 0
R/W — LPC Busy
Indicates that the host interface is processing a
transfer cycle.
0: Host interface is in transfer cycle wait state
• Bus idle, or transfer cycle not subject to
processing is in progress
• Cycle type or address indeterminate during
transfer cycle
[Clearing conditions]
• LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software
shutdown
• Forced termination (abort) of transfer cycle
subject to processing
• Normal termination of transfer cycle subject to
processing
1: Host interface is performing transfer cycle
processing
[Setting condition]
• Match of cycle type and address
Rev. 2.0, 08/02, page 511 of 788