HD64F2145 Datasheet, PDF (129/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.3.2 Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit Bit Name Initial Value R/W
7
CMF
0
R
6
—
All 0
R
to
1
0
BIE
0
R/W
Description
Condition Match Flag
Address break source flag. Indicates that an
address specified by BARA to BARC is
prefetched.
[Setting condition]
When an address specified by BARA to BARC
is prefetched while the BIE flag is set to 1.
[Clearing condition]
When an exception handling is executed for an
address break interrupt.
Reserved
These bits are always read as 0 and cannot be
modified.
Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
5.3.3 Break Address Registers A to C (BARA to BARC)
The BAR registers specify an address that is to be a break address. An address in which the first
byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to
A16 are not compared.
• BARA
Bit Bit Name Initial Value R/W
7
A23
All 0
R/W
to
to
0
A16
Description
Addresses 23 to 16
The A23 to A16 bits are compared with A23 to
A16 in the internal address bus.
Rev. 2.0, 08/02, page 89 of 788