HD64F2145 Datasheet, PDF (590/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 19.8 summarizes the methods of setting and clearing these bits, and figure 19.8 shows the
processing flowchart.
Table 19.8 HIRQ Setting and Clearing Conditions
Host Interrupt Setting Condition
Clearing Condition
HIRQ1
(independent
from IEDIR)
Internal CPU writes to ODR1, then reads Internal CPU writes 0 to bit IRQ1E1,
0 from bit IRQ1E1 and writes 1
or host reads ODR1
HIRQ12
(independent
from IEDIR)
Internal CPU writes to ODR1, then reads Internal CPU writes 0 to bit IRQ12E1,
0 from bit IRQ12E1 and writes 1
or host reads ODR1
SMI
(IEDIR = 0)
Internal CPU
Internal CPU
• writes to ODR2, then reads 0 from bit • writes 0 to bit SMIE2, or host
SMIE2 and writes 1
reads ODR2
• writes to ODR3, then reads 0 from bit • writes 0 to bit SMIE3A, or host
SMIE3A and writes 1
reads ODR3
• writes to TWR15, then reads 0 from • writes 0 to bit SMIE3B, or host
bit SMIE3B and writes 1
reads TWR15
SMI
(IEDIR = 1)
Internal CPU
Internal CPU
• reads 0 from bit SMIE2, then writes 1 • writes 0 to bit SMIE2
• reads 0 from bit SMIE3A, then writes • writes 0 to bit SMIE3A
1
• writes 0 to bit SMIE3B
• reads 0 from bit SMIE3B, then writes
1
HIRQi
(i = 6, 9, 10, 11)
(IEDIR = 0)
Internal CPU
Internal CPU
• writes to ODR2, then reads 0 from bit • writes 0 to bit IRQiE2, or host
IRQiE2 and writes 1
reads ODR2
• writes to ODR3, then reads 0 from bit • CPU writes 0 to bit IRQiE3, or
IRQiE3 and writes 1
host reads ODR3
HIRQi
(i = 6, 9, 10, 11)
(IEDIR = 1)
Internal CPU
Internal CPU
• reads 0 from bit IRQiE2, then writes 1 • writes 0 to bit IRQiE2
• reads 0 from bit IRQiE3, then writes 1 • writes 0 to bit IRQiE3
Rev. 2.0, 08/02, page 550 of 788