HD64F2145 Datasheet, PDF (588/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

19.4.6 Host Interface Clock Start Request (CLKRUN)
A request to restart the clock (LCLK) can be sent to the host processor by means of the &/.581
pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested
since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host
interrupt request is generated the &/.581 signal is driven and a clock (LCLK) restart request is
sent to the host. The timing for this operation is shown in figure 19.7.
CLK
1
2
3
4
5
6
Pull-up enable
Drive by the slave processor
Drive by the host processor
Figure 19.7 Clock Start Request Timing
Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a
different protocol, using the 30( signal, etc.
19.5 Interrupt Sources
19.5.1 IBFI1, IBFI2, IBFI3, and ERRI
The host interface has four interrupt requests for the slave processor (this LSI): IBF1, IBF2, IBF3,
and ERRI. IBFI1, IBFI2, and IBFI3 are IDR receive complete interrupts for IDR1, IDR2, and
IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such
as an LPC reset, LPC shutdown, or transfer cycle abort. An interrupt request is enabled by setting
the corresponding enable bit.
Table 19.7 Receive Complete Interrupts and Error Interrupt
Interrupt
IBFI1
IBFI2
IBFI3
ERRI
Description
When IBFIE1 is set to 1 and IDR1 reception is completed
When IBFIE2 is set to 1 and IDR2 reception is completed
When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and
IBFIE3 are set to 1 and reception is completed up to TWR15
When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1
Rev. 2.0, 08/02, page 548 of 788