HD64F2145 Datasheet, PDF (344/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit
Bit Name Initial Value R/W Description
3
HOINV
0
R/W Output Synchronization Signal Inversion
2
VOINV
0
1
CLOINV 0
0
CBOINV 0
R/W These bits select inversion of the output phase of the
R/W ^{horizontal synchronization signal (HSYNCO), the}
vertical synchronization signal (VSYNCO), the clamp
R/W _{waveform (CLAMPO), and the blanking waveform}
(CBLANK).
• HOINV:
0: The IHO signal is used directly as the HSYNCO
output
1: The IHO signal is inverted before use as the
HSYNCO output
• VOINV:
0: The IVO signal is used directly as the VSYNCO
output
1: The IVO signal is inverted before use as the
VSYNCO output
• CLOINV:
0: The CLO signal (CL1, CL2, CL3, or CL4 signal) is
used directly as the CLAMPO output
1: The CLO signal (CL1, CL2, CL3, or CL4 signal) is
inverted before use as the CLAMPO output
• CBOINV:
0: The CBLANK signal is used directly as the CBLANK
output
1: The CBLANK signal is inverted before use as the
CBLANK output
Rev. 2.0, 08/02, page 304 of 788