HD64F2145 Datasheet, PDF (101/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Prior to executing BCLR:
Input/output
Pin state
DDR
DR
P47
Input
Low
level
0
1
P46
Input
High
level
0
0
P45
Output
Low
level
1
0
P44
Output
Low
level
1
0
P43
Output
Low
level
1
0
P42
Output
Low
level
1
0
P41
Output
Low
level
1
0
P40
Output
Low
level
1
0
BCLR instruction executed:
BCLR #0, @P4DDR
The BCLR instruction is executed for DDR in port 4.
After executing BCLR:
Input/output
Pin state
DDR
DR
P47
Output
Low
level
1
1
P46
Output
High
level
1
0
P45
Output
Low
level
1
0
P44
Output
Low
level
1
0
P43
Output
Low
level
1
0
P42
Output
Low
level
1
0
P41
Output
Low
level
1
0
P40
Input
High
level
0
0
Operation:
1. When the BCLR instruction is executed, first the CPU reads P4DDR.
Since P4DDR is a write-only register, so the CPU reads H’FF. In this example P4DDR has a
value of H'3F, but the value read by the CPU is H'FF.
2. The CPU clears bit 0 of the read data to 0, changing data to H'FE.
3. The CPU writes H'FE to DDR, completing execution of BCLR.
As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin.
However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins.
Rev. 2.0, 08/02, page 61 of 788