HD64F2145 Datasheet, PDF (372/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.4 Operation
14.4.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/,7 bit and the TME bit in TCSR to 1. While the
WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a
system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
If the RST/10, bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this
LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the
5(62 pin for 132 states, as shown in figure 14.2. If the RST/10, bit is cleared to 0, when the
TCNT overflows, an NMI interrupt request is generated. Here, the output from the 5(62 pin
remains high.
An internal reset request from the watchdog timer and a reset input from the 5(6 pin are
processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If
a reset caused by a signal input to the 5(6 pin occurs at the same time as a reset caused by a WDT
overflow, the 5(6 pin reset has priority and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Rev. 2.0, 08/02, page 332 of 788