HD64F2145 Datasheet, PDF (560/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

19.3.7 Status Registers 1 to 3 (STR1 to STR3)
The STR registers are 8-bit registers that indicate status information during host interface
processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits for both
the host processor and the slave processor (this LSI). However, only 0 can be written to bit 0 of
STR1 to STR3 and bits 6 and 4 of STR3, from the slave processor (this LSI), in order to clear the
flags to 0. The registers selected from the host processor according to the I/O address are shown in
the following table. For information on STR3 selection, see section 19.3.3, LPC Channel 3
Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is
transferred to the host processor. The initial values of STR1 to STR3 are H’00.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
I/O Address
Bit 3 Bit 2
0
1
0
1
Bit 1
0
1
Bit 0
0
0
Transfer
Cycle
I/O read
I/O read
Host Register Selection
STR1 read
STR2 read
Rev. 2.0, 08/02, page 520 of 788