HD64F2145 Datasheet, PDF (378/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.6.5 System Reset by 5(62 Signal
Inputting the 5(62 output signal to the 5(62 pin of this LSI prevents the LSI from being
initialized correctly; the 5(62 signal must not be logically connected to the 5(6 pin of the LSI.
To reset the entire system by the 5(62 signal, use the circuit as shown in figure 14.8.
This LSI
Figure 14.8 Sample Circuit for Resetting System by 5(62 Signal
14.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch
Modes
When WDT_1 is used as a clock counter and is allowed to transit between high-speed mode and
sub-active or watch mode, the counter does not display the correct value due to internal clock
switching.
Specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the
control clock for WDT_1 switches from the main clock to the sub-clock, the counter incrementing
timing is delayed for approximately two to three clock cycles.
Similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not
supplied until stabilized internal oscillation is available because the main clock oscillator is halted
in sub-clock mode. The counter is therefore prevented from incrementing for the time specified by
the STS2 to STS0 bits in SBYCR after internal oscillation starts, thus producing counter value
differences for this time.
Special care must be taken when using WDT_1 as a clock counter. Note that no counter value
difference is produced while operated in the same mode.
Rev. 2.0, 08/02, page 338 of 788