HD64F2145 Datasheet, PDF (817/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Page Revisions (See Manual for Details)
Section 19 Host Interface 503,
LPC Interface (LPC)
517,
518,
523
(Error) Two-way register
(Correction) Bidirectional data register
19.3 Register Descriptions 506 Description added.
The LPC has the following registers. The settings of XBS
related bits do not affect the operation of this LSI’s LPC.
However, for reasons relating to the configuration of the
program development tool (emulator), when the LPC is used,
bit HI12E in SYSCR2 should not be set to 1. For details, see
section 3.2.2, System Control Register (SYSCR), and section
18.3.1, System Control Register 2 (SYSCR2).
19.3.4 Input Data
519
Registers (IDR1 to IDR3)
Description added.
The initial values of IDR1 to IDR3 are undefined.
19.3.5 Output Data
Registers (ODR1 to
ODR3)
519 Description added.
The initial values of ODR1 to ODR3 are undefined.
19.3.6 Bidirectional Data 520
Registers (TWR0 to
TWR15)
Description added.
The initial values of TWR0 to TWR15 are undefined.
19.3.7 Status Registers 520 Description added
(STR1 to STR3)
The initial values of STR1 to STR3 are H'00.
19.6.1 Module Stop Mode 551 Added.
Setting
Section 20 D/A Converter 554 Description added.
20.3.1 D/A Data Registers
0 and 1 (DADR0, DADR1)
DADR0 and DADR1 are initialized to H'00.
20.5.1 Module Stop Mode 557 Added.
Setting
Section 21 A/D Converter 559 (Error)
21.1 Features
• Module stop mode can be set
(Correction)
Deleted.
Rev. 2.0, 08/02, page 777 of 788