HD64F2145 Datasheet, PDF (497/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 16.11 I²C Bus Timing (with Maximum Influence of t_Sr/t_Sf)
Item
t_cyc
Indication
Time Indication (at Maximum Transfer Rate) [ns]
I²C Bus
t_Sr/t_Sf
Specifi-
Influence cation ø = ø =
(Max.) (Min.) 5 MHz 8 MHz
ø=
10 MHz
ø=
ø=
16 MHz 20 MHz
t_SCLHO
0.5 t_SCLO (–t_Sr) Standard mode –1000
High-speed mode –300
4000
600
4000 4000
950 950
4000
950
4000
950
4000
950
t_SCLLO
0.5 t_SCLO (–t_Sf) Standard mode –250
High-speed mode –250
4700
1300
4750 4750 4750
1000*¹ 1000*¹ 1000*¹
4750 4750
1000*¹ 1000*¹
t_BUFO
0.5 t_SCLO –1 t_cyc Standard mode –1000
4700
3800*¹ 3875*¹ 3900*¹
3938*¹ 3950*¹
(–t_Sr)
High-speed mode –300
1300 750*¹ 825*¹ 850*¹
888*¹ 900*¹
t_STAHO
0.5 t_SCLO –1 t_cyc Standard mode –250
(–t_Sf)
High-speed mode –250
4000
600
4550 4625
800 875
4650
900
4688
938
4700
950
t_STASO
1 t_SCLO (–t_Sr)
Standard mode –1000
High-speed mode –300
4700
600
9000 9000
2200 2200
9000
2200
9000
2200
9000
2200
t_STOSO
0.5 t_SCLO + 2 t_cyc Standard mode –1000
(–t_Sr)
High-speed mode –300
4000
600
4400 4250
1350 1200
4200
1150
4125
1075
4100
1050
t_SDASO
1
t *3
SCLLO
–3
t_cyc
Standard
mode
–1000
250
(master) (–t_Sr)
High-speed mode –300
100
3100 3325
400 625
3400
700
3513
813
3550
850
t_SDASO
(slave)
1
t *3
SCLL
–12
t *2
cyc
(–t_Sr)
Standard mode –1000 250
High-speed mode –300
100
1300 2200 2500
2950 3100
–1400 –500*¹ –200*¹ 250
400
*¹
t_SDAHO
3 t_cyc
Standard mode 0
0
600 375
300
188 150
High-speed mode 0
0
600 375
300
188 150
Notes: 1. Does not meet the I²C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I²C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t –
SCLL
6t_cyc).
3. Calculated using the I²C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
7. Notes on ICDR read at end of master reception
Rev. 2.0, 08/02, page 457 of 788