HD64F2145 Datasheet, PDF (377/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.6.2 Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 14.7 shows this operation.
TCNT write cycle
T₁
T₂
ø
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 14.7 Conflict between TCNT Write and Increment
14.6.3 Changing Values of CKS2 to CKS0 Bits
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
Rev. 2.0, 08/02, page 337 of 788