HD64F2145 Datasheet, PDF (608/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

21.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t_D) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 21.3 shows the A/D conversion timing. Table 21.3 indicates
the A/D conversion time.
As indicated in figure 21.3, the A/D conversion time (t_CONV) includes t_D and the input sampling time
(t_SPL). The length of t_D varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 21.3.
In scan mode, the values given in table 21.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 256 state (fixed) when CKS = 0 and 128 states
(fixed) when CKS = 1.
(1)
ø
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
Legend
(1) : ADCSR write cycle
(2) : ADCSR address
t_D : A/D conversion start delay
t_SPL : Input sampling time
t_CONV : A/D conversion time
Figure 21.3 A/D Conversion Timing
Rev. 2.0, 08/02, page 568 of 788