HD64F2145 Datasheet, PDF (647/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Section 24 Masked ROM
This series incorporates a 64-kbyte or 128-kbyte masked ROM. The on-chip ROM is connected to
the CPU and data transfer controller (DTC) via the 16-bit data bus. The CPU and DTC can access
the on-chip ROM with 8- or 16-bit width. Data in the on-chip ROM can always be accessed in one
state.
Internal data bus (upper 8 bits)
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'000001
H'000003
Internal data bus (lower 8 bits)
H'0000
H'0002
H'0001
H'0003
H'01FFFE
H'01FFFF
H'DFFE
H'DFFF
Mode 2
Mode 3
Figure 24.1 Block Diagram of 128-Kbyte Masked ROM (HD6432161BV)
Internal data bus (upper 8 bits)
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'000001
H'000003
Internal data bus (lower 8 bits)
H'0000
H'0002
H'0001
H'0003
H'00FFFE
H'00FFFF
Mode 2
H'DFFE
H'DFFF
Mode 3
Figure 24.2 Block Diagram of 64-Kbyte Masked ROM (HD6432160BV)
The on-chip ROM is enabled or disabled according to the operating mode. The operating mode is
selected by the mode select pins MD1 and MD0 as indicated in table 3.1. Select mode 2 or 3 to
enable the on-chip ROM; whereas mode 1 to disable the on-chip ROM. The on-chip ROM is
allocated in area 0.
Rev. 2.0, 08/02, page 607 of 788