HD64F2145 Datasheet, PDF (294/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ø
External clock
input pin
FRC input
clock
FRC
N
N+1
Figure 11.4 Increment Timing with External Clock Source
11.5.2 Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). When a compare-match signal occurs, the level
selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure
11.5 shows the timing of this operation for compare-match A.
ø
FRC
OCRA
N
N+1
N
N
N+1
N
Compare-match
A signal
OLVLA
Clear*
Output compare A
output pin FTOA
Note : * Indicates instruction execution by software.
Figure 11.5 Timing of Output Compare A Output
Rev. 2.0, 08/02, page 254 of 788