HD64F2145 Datasheet, PDF (816/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
16.4.9 Operation Using
DTC
Table 16.7 Examples of
Operation Using DTC
Page Revisions (See Manual for Details)
451 (Error)
(Correction)
Slave
Master
Transmit
Item
Transmit Mode Mode
Item
Master
Transmit
Mode
Slave
Transmit
Mode
Transfer
request
processing
after last
frame
processing
1st time:
Clearing by
CPU
2nd time: End
condition
issuance by
CPU
Automatic
clearing on
detection of
end
condition
during
transmission
of dummy
data (H'FF)
Transfer
1st time:
request
Clearing by
processing
CPU
after last frame
2nd time:
processing
Stop
condition
issuance by
CPU
Automatic
clearing on
detection of
stop condition
during
transmission
of dummy
data (H'FF)
16.6 Usage Notes
457
Table 16.11 I²C Bus
Timing (with Maximum
Influence of tsr/tsf )
16.6.1 Module Stop Mode 463
Setting
Section 17 Keyboard
467
Buffer Controller
17.3 Register Descriptions
17.5 Usage Notes
481
17.5.2 Module Stop Mode
Setting
Section 18 Host Interface 483
X-Bus Interface (XBS)
18.1 Features
18.6 Usage Notes
501
18.6.2 Module Stop Mode
Setting
(Error)
Item
t (slave)
SDASO
Notes:
2.
3.
Added.
(Correction)
t_cyc Indication
Item
t_cyc Indication
1
t *3
SCLL
–3
t_cyc*²(–t_Sr
)
t (slave)
SDASO
1
t *3
SCLL
–12
t_cyc*²(–t_Sr )
Value when the IICX bit is set to 1. When the IICX bit is cleared to
0, the value is (t – 6t ).
SCLL
cyc
Calculated using the I²C bus specification values (standard mode:
4700 ns min.; high-speed mode: 1300 ns min.).
Description deleted.
The keyboard buffer controller has the following registers for
each channel. For details on the module stop control register,
refer to section 26.1.3, Module Stop Control Registers H and L
(MSTPCRH, MSTPCRL).
Added.
(Error)
• Module stop mode setting
(Correction)
Deleted.
Added.
Rev. 2.0, 08/02, page 776 of 788