HD64F2145 Datasheet, PDF (668/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Oscillator
ø
NMI
NMIEG
SSBY
NMI exception
Software standby mode
handling
(power-down mode)
NMIEG = 1
SSBY = 1
SLEEP instruction
Oscillation
stabilization
time t_OSC2
NMI exception
handling
Figure 26.3 Application Example in Software Standby Mode
26.6 Hardware Standby Mode
The CPU makes a transition to hardware standby mode from any mode when the 67%< pin is
driven low.
In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is
supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the 67%< pin low. Do not change the state of the mode pins (MD1 and MD0) while this
LSI is in hardware standby mode.
Hardware standby mode is cleared by the 67%< pin input or the 5(6 pin input.
When the 67%< pin is driven high while the 5(6 pin is low, clock oscillation is started. Ensure
that the 5(6 pin is held low until system clock oscillation stabilizes. When the 5(6 pin is
subsequently driven high after the clock oscillation stabilization time has passed, reset exception
handling starts.
Rev. 2.0, 08/02, page 628 of 788