HD64F2145 Datasheet, PDF (270/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

10.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB)
DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since
DADR consists of 16-bit data, DADR transfers data to the CPU via the temporary register
(TEMP). For details, refer to section 10.4, Bus Master Interface.
• DADRA
Bit Bit Name
15 DA13
14 DA12
13 DA11
12 DA10
11 DA9
10 DA8
9 DA7
8 DA6
7 DA5
6 DA4
5 DA3
4 DA2
3 DA1
2 DA0
1 CFS
0—
Initial Value R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R
Description
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
keeping the two lowest data bits (DA1 and DA0) cleared
to 0. The two lowest data bits correspond to the two
highest bits in DACNT.
Carrier Frequency Select
0: Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1: Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
Reserved
This bit is always read as 1 and cannot be modified.
Rev. 2.0, 08/02, page 230 of 788