HD64F2145 Datasheet, PDF (467/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Start
Initialize IIC
[1] Initialization
Read BBSY flag in ICCR
No
BBSY = 0?
Yes
Set MST = 1 and
TRS = 1 in ICCR
Set BBSY =1 and
SCP = 0 in ICCR
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Write transmit data in ICDR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Read ACKB bit in ICSR
ACKB = 0?
No
Yes
Transmit mode?
No
Yes
Write transmit data in ICDR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Read ACKB bit in ICSR
No
End of transmission?
or ACKB = 1?
Yes
Clear IRIC flag in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
End
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte
(slave address + R/ ).
(After writing to ICDR, clear IRIC flag
continuously.)
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit
transferred from the slave device.
Master receive mode
[9] Set transmit data for the second and
subsequent bytes.
(After writing to ICDR, clear IRIC flag
continuously.)
[10] Wait for 1 byte to be transmitted.
[11] Determine end of tranfer
[12] Stop condition issuance
Figure 16.8 Sample Flowchart for Operations in Master Transmit Mode
Rev. 2.0, 08/02, page 427 of 788