HD64F2145 Datasheet, PDF (584/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

The scope of the initialization in each mode is shown in table 19.6.
Table 19.6 Scope of Initialization in Each Host Interface Mode
Items Initialized
System
LPC
Reset
LPC Reset Shutdown
LPC transfer cycle sequencer (internal state), LPCBSY Initialized Initialized
and ABRT flags
Initialized
SERIRQ transfer cycle sequencer (internal state),
CLKREQ and IRQBSY flags
Initialized Initialized Initialized
Host interface flags
(IBF1, IBF2, IBF3A, IBF3B, MWMF, C/'1, C/'2, C/'3,
OBF1, OBF2, OBF3A, OBF3B, SWMF, DBU), GA20
(internal state)
Initialized Initialized
Retained
Host interrupt enable bits
Initialized
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2,
IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3
to IRQ11E3), Q/& flag, SELREQ bit
Initialized
Retained
LRST flag
Initialized Can be
Can be
(0)
set/cleared set/cleared
SDWN flag
Initialized Initialized
(0)
(0)
Can be
set/cleared
LRSTB bit
Initialized HR: 0
(0)
SR: 1
0 (can be
set)
SDWNB bit
Initialized Initialized
(0)
(0)
HS: 0
SS: 1
SDWNE bit
Initialized Initialized
(0)
(0)
HS: 1
SS: 0 or 1
Host interface operation control bits
Initialized
(LPC3E to LPC1E, FGA20E, LADR3,
IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB, LSCIE,
LSCIB, TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ6,
SELIRQ9, SELIRQ10, SELIRQ11, SELIRQ12)
Retained
Retained
/5(6(7 signal
Input (port Input
function
Input
/3&3' signal
Input
Input
LAD3 to LAD0, /)5$0(, LCLK, SERIRQ,
&/.581 signals
30(, /60,, LSCI, GA20 signals (when function
is selected)
Input
Hi-Z
Output
Hi-Z
30(, /60,, LSCI, GA20 signals (when function
is not selected)
Port function Port function
Note: System reset: Reset by STBY input, RES input, or WDT overflow
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
Rev. 2.0, 08/02, page 544 of 788